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DTSTART;TZID=Europe/Berlin:20211124T090000
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DTSTAMP:20260526T020805
CREATED:20211005T124707Z
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SUMMARY:[:en]Programming for the NEC SX-Aurora TSUBASA Vector Engine[:]
DESCRIPTION:Introduction\nThe NEC SX-Aurora TSUBASA is a new vector processor based accelerator for HPC workloads. Since this vector engine (VE) provides a very high memory bandwidth\, it is a very promising architecture for memory bound applications. The VE is provided as a PCIe card in a x86-64 server. Each VE is equipped with 8 to 10 cores. This workshop provides detailed information about the Aurora Architecture and the programming opportunities. Experts from NEC will present the programming environment and the different  execution models including hints for performance tuning. \nDetails\nDate: 24th November 2021\nLocation: Online\nOrganizer: NEC and RWTH Aachen University \n\nAgenda\n\n\n\n\n\nTime\n\n\n\n\nTopic\n\n\n\nSpeaker\n\n\n\n09:00 – 09:05\nWelcome\nRWTH and NEC\n\n\n09:00 – 10:00\nIntroduction to SX-Aurora TSUBASA\nErich Focht (NEC)\n\n\n10:15 – 11:15\nIntroduction to Vector Computing I\nFelix Uhl (NEC)\n\n\n11:20 – 12:50\nOpenMP Offloading for SX-Aurora TSUBASA\nTim Cramer (RWTH)\n\n\n12:50 – 14:00\nBreak\n\n\n\n14:00 – 15:00\nIntroduction to Vector Computing II\nChristian Weiss (NEC)\n\n\n15:00 – 15:30\nHybrid MPI Usage\nFelix Uhl (NEC)\n\n\n15:30 – 15:45\nClosing Session\n\n\n\n\n\nRegistration\nhttps://terminplaner4.dfn.de/iTPZUtfIYJDVfGW6 \nContact\nTim Cramer\nhpcevent@itc.rwth-aachen.de
URL:https://blog.rwth-aachen.de/itc-events/en/event/programming-for-the-nec-sx-aurora-tsubasa-vector-engine/
LOCATION:Online\, Deutschland
CATEGORIES:Einmalig,HPC Events
ORGANIZER;CN="HPC":MAILTO:hpcevent@itc.rwth-aachen.de
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