Introduction into Claix 2016 and Tuning Workshop Wed, November 30 – Fri, December 2, 2016 IT Center RWTH Aachen University sponsored by:

Introduction

Claix2016, the first stage of Claix, short for Cluster Aix-la-Chapelle, has been integrated into the RWTH Compute Cluster by NEC and went into production in November 2016.
Therefore,  we want to begin this year’s tuning workshop aiXcelerate 2016 with some introductory presentations before we then focus on tuning selected compute projects for the new machinery.
We are proud to announce HPC performance experts  Michael Klemm and Christopher Dahnken from Intel and René Puttin, Daniel Tameling, and Fredrik Unger from NEC to be available for the whole workshop. They will be complemented by experts of the HPC Team of the IT Center at RWTH Aachen University.

Presentations will be given in English.

Materials

• Agenda – please find   agenda here >>>  
  PART I – 30.11.2016
  
• 01. C.Terboven: Opening
• 02. F. Unger, NEC: CLAIX
• 03. C.Dahnken, Intel: Omni-Path and Intel MPI
• 04. C.Dahnken, Intel: Broadwell and Knights Landing (KNL)
• 05. M.Klemm, Intel: Intel Tools
• 06. M.Klemm, Intel: SIMD Vectorization with OpenMP
• 07. P.Kapinos, IT Center: Claix-HowTo
  PART II – 01.12.2016
• 08. M.Klemm, Intel: Performance Analysis in a Nutshell
  
• 09. R.Puttin, NEC:  Cache
•  10. R.Puttin, NEC:  Report and Directives
  PART II – 02.12.2016
• 11. M.Klemm, Intel: Transactional Memory
• 12. C.Dahnken, Intel: LIBXSMM for CP2K
  

PART I – open to everyone

On Wed, Nov 30, 10:00 – 16:00 we are pleased to welcome experts from NEC and Intel to give an overview into the configuration and the main components of the new HPC cluster and their usage.
Agenda items will include introduction into overall configuration, Intel OmniPath network, Intel Broadwell and Intel Knights Landing processors.
Furthermore, Intel software tools for performance tuning, targeted for these new components, will be introduced and demonstrated.

This part of aiXcelerate is primarily directed towards any possible user of Claix-2016.

Please  register here >>> for PART I of aiXcelerate 2016.

PART II – upon special invitation only

The main part of the aiXcelerate 2016 Tuning Workshop will focus on adaptation and performance tuning of selected compute projects upon special invitation only.
Members of approved compute projects for the JARA-HPC partition will be given priority.

Given the trend of modern Processors to contain more and more cores and wider vector units, it becomes increasingly important to optimize code for these architectures to utilize the processor in an efficient way.
In our recent tutorial(s), e.g. the  PPCES 2016 event, we discussed MPI and OpenMP parallelization in detail and already some optimization techniques and tools suitable to optimize for single node performance. In this workshop, we will take a very detailed look at these topics and invite code projects to work together with experts on single node optimization and also on adaption to the new Intel OmniPath network.

This “bring-in your own code” workshop aims for you to participate with your own application code and optimize the code during the workshop with help from the HPC experts. The workshop will contain some talks presenting tools and techniques for code optimization, but most of the time is reserved for code work on the RWTH Aachen compute cluster.

As we plan to accommodate several representatives from the user community, we will have to time slice between the participants. Where needed, we will give advice and then ask you to try it, while we work with other attendees. Performance tuning is still a matter of some experimentation, but we can give you advice on a best effort basis. Hopefully this will lead to a noticeable performance improvement, but guarantees cannot be given.

The first hands-on session for porting and analyzing application codes starts on Wed, Nov 30, 16:00. During the following two days we will start at 9:00 in the morning and finish at about 17:30 in the afternoon. Thursday, Dec 01 will end with an social dinner sponsored by ho-computers.

Prerequisites and your Preparation in PART II

Attendees are kindly requested to prepare and bring in their own code. It is assumed that you have a good working knowledge with MPI and/or OpenMP, and C/C++ or Fortran, whatever your compute project employs. To maximize the efficiency of the workshop, we would like to ask you to prepare one or more test cases that reflect typical production runs, but do not take too long to execute – in the ideal case, a run should not take more than 5 to 10 minutes to finish. Members of the local HPC team will support  every accepted project in porting the code to the new machines of the RWTH Compute Cluster. By the start of the workshop the code should be ready to be analyzed.

Claix-2016 consists mainly of two node types:

(1) CLAIX2016-MPI: 600+ nodes have two Intel Xeon E5-2650v4 (Broadwell) processors (2,2 GHz, 12 cores each) with 24 cores in total and 128 GB main memory.

(2) CLAIX2016-SMP: 8 nodes comprise eight Intel Xeon E7-8860v4 (Broadwell) processors (2,2 GHz, 18 cores each) each node has 144 cores in total and 1024 GB main memory.

The machines are all integrated into the RWTH Compute Cluster which is currently operated under CentOS 7.2 Linux, so all codes need to run there.

Furthermore, we ordered some additional compute nodes equipped with 64 core Xeon Phi Knights Landing processors (KNL). But presumably those will not yet be available at the time of the tuning workshop.
Most likely only one KNL system will be available on site for the workshop.

Please, take these boundary conditions into consideration when preparing your test cases.