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Programming for the NEC SX-Aurora TSUBASA Vector Engine
Wednesday, 24. November 2021 ► 9:00 - 15:45
Introduction
The NEC SX-Aurora TSUBASA is a new vector processor based accelerator for HPC workloads. Since this vector engine (VE) provides a very high memory bandwidth, it is a very promising architecture for memory bound applications. The VE is provided as a PCIe card in a x86-64 server. Each VE is equipped with 8 to 10 cores. This workshop provides detailed information about the Aurora Architecture and the programming opportunities. Experts from NEC will present the programming environment and the different execution models including hints for performance tuning.
Details
Date: 24th November 2021
Location: Online
Organizer: NEC and RWTH Aachen University
Agenda
Time |
Topic |
Speaker
|
|---|---|---|
| 09:00 – 09:05 | Welcome | RWTH and NEC |
| 09:00 – 10:00 | Introduction to SX-Aurora TSUBASA | Erich Focht (NEC) |
| 10:15 – 11:15 | Introduction to Vector Computing I | Felix Uhl (NEC) |
| 11:20 – 12:50 | OpenMP Offloading for SX-Aurora TSUBASA | Tim Cramer (RWTH) |
| 12:50 – 14:00 | Break | |
| 14:00 – 15:00 | Introduction to Vector Computing II | Christian Weiss (NEC) |
| 15:00 – 15:30 | Hybrid MPI Usage | Felix Uhl (NEC) |
| 15:30 – 15:45 | Closing Session |
Registration
https://terminplaner4.dfn.de/iTPZUtfIYJDVfGW6
Contact
Tim Cramer
hpcevent@itc.rwth-aachen.de
