Source: SC21
The largest HPC conference in the world and we are a part of it
This year at SC21, from November 14-19, thousands of researchers, developers, students, exhibitors, managers, and speakers from institutes of all shapes and sizes will gather to share ideas about the power of high performance computing (HPC) and discover the latest innovations. There are opportunities in St. Louis to attend the conference on-site or to experience SC Remote.
This year’s theme is “Science & Beyond.” True to this, the SC community is committed to providing attendees with insight into how HPC is moving beyond the scientific and academic communities into other industries and improving research and business outcomes. Particularly in the commercial sector, HPC is becoming increasingly popular, such that HPC and supercomputing technologies are being used to advance a range of products. These include the development of vaccines to the design of autonomous vehicles. “Science & Beyond” therefore means that HPC can be used in a range of use cases to tackle the world’s biggest challenges, discover new things and open up new frontiers.
Participants can expect a diverse program onsite and online in the form of live demos, talks and tutorials in the areas of artificial intelligence, exascale computing, container software and much more. Our HPC team will also be there remotely, enriching the program with tutorials and scientific talks.
Mastering Tasking with OpenMP
Sunday, 14 November 20218am – 5pm CST
Christian Terboven, Michael Klemm, Xavier Teruel
The tutorial looks at rethinking the development and structuring of code in the use of the so-called tasking concept with OpenMP. The concept allows the creation of composable parallel software blocks and thus the parallelization of irregular algorithms.
Advanced OpenMP: Host Performance and 5.1 Features
Monday, 15 November 20218am – 5pm CST
Christian Terboven, Michael Klemm, Ruud van der Pas
This tutorial will focus on the correctness and performance implications of possible OpenMP parallelization strategies, such as data and thread locality on NUMA architectures and the use of vector units.
Scientific talk at the HiPar workshop
“PPIR: Parallel Pattern Intermediate Representation”
Sunday, 14 November 20219am – 5:30pm CST
Adrian Schmitz, Julian Miller, Lukas Trümper, Matthias Müller
HPC systems are becoming increasingly larger, more heterogeneous, and thus more complex to meet the growing demands of science and engineering. To exploit the full performance potential from these systems, system- and architecture-specific optimizations are necessary. One approach is to use parallel patterns to develop structured code that can be automatically optimized. The presented approach is based on global optimizations that optimize the data flow over the entire parallel algorithm and determine an efficient allocation of computational operations to available resources.
The presented paper introduces a fast and compact intermediate representation for parallel pattern-based applications and serves as a basis for the global optimizations. For this purpose, the hierarchical tree structure “Abstract Pattern Tree (APT)” is presented and implemented in a prototype compiler. This prototype allows 17 of the 19 applications of the Rodinia Benchmark Suite to be represented and analyzed using a few parallel patterns. In doing so, the original code was strongly summarized by the parallel patterns, which improves programming productivity. Furthermore, the prototype shows short compile times for most benchmarks.
Scientific presentation at the Protools Workshop
“Differential Performance Analysis Workflow for Algorithmic Changes”
Sunday, 14 November 20219am – 5:30pm CST
Isabel Thärigen, Joachim Protze, Fabian Orland, Marc-André Hermanns
Most performance analysis tools focus on the analysis of a single configuration of an application. However, different code variants of a single application often exist if certain parts are implemented by different algorithms or by using third-party software libraries. Similarly, different parameters such as the number of execution units or the input data can be varied. Both types of variation have an impact on the performance of the application.
Therefore, in this work we present a new workflow which allows the comparison of different code versions as well as different parameters for the execution of the application. Our workflow is based on the benchmark environment “JUelich Benchmarking Environment” (JUBE), which can automatically perform a variety of measurements including data collection after initial manual configuration. We also present special diagrams for clear and precise visualization of the measurement data. Finally, we show through case studies of two applications CalculiX and JuKKR that our workflow enables detailed performance analysis and is still easy to use.
Scientific presentation at the PDSW workshop
“User-Centric System Fault Identification Using IO500 Benchmark”
Monday, 15 November 20219am – 5:30pm CST
Radita Liem, Dmytro Povaliaiev, Jay Lofstead, Julian Kunkel, Christian Terboven
Predicting the performance of IO operations on current HPC systems where users competitively saturate the IO infrastructure is a major challenge. The first step towards this is to measure IO performance on HPC storage systems, which can be done using the IO500 benchmark.
This scientific talk presents a first step for a user-centric workflow that will be evaluated on the RWTH cluster CLAIX-2018. It is based on measurements of the IO500 benchmark and aims to optimize the IO performance. For this purpose, the best- and worst-case performance results for bandwidth and metadata rate are determined using the IO500 benchmark and presented as a bounding box. Users’ HPC applications are mapped within this box, illustrating the potential and direction of individual IO optimization.
Scientific talk at the Correctness Workshop
“Understanding the Performance of Dynamic Data Race Detection”
Friday, 19 November 202110:30am – 10:50am CST
Joachim Protze, Isabel Thärigen, Jonas Wahle
The presented paper introduces a fast and compact intermediate representation for parallel pattern-based applications and serves as a basis for the global optimizations. For this purpose, the hierarchical tree structure “Abstract Pattern Tree (APT)” is presented and implemented in a prototype compiler. This prototype allows 17 of the 19 applications of the Rodinia Benchmark Suite to be represented and analyzed using a few parallel patterns. In doing so, the original code was strongly summarized by the parallel patterns, which improves programming productivity. Furthermore, the prototype shows short compile times for most benchmarks.
Scientific presentation at the Protools Workshop
Differential Performance Analysis Workflow for Algorithmic Changes”
Sunday, 14 November 20219am – 5:30pm CST
Isabel Thärigen, Joachim Protze, Fabian Orland, Marc-André Hermanns
Most performance analysis tools focus on the analysis of a single configuration of an application. However, different code variants of a single application often exist if certain parts are implemented by different algorithms or by using third-party software libraries. Similarly, different parameters such as the number of execution units or the input data can be varied. Both types of variation have an impact on the performance of the application.
Therefore, in this work we present a new workflow which allows the comparison of different code versions as well as different parameters for the execution of the application. Our workflow is based on the benchmark environment “JUelich Benchmarking Environment” (JUBE), which can automatically perform a variety of measurements including data collection after initial manual configuration. We also present special diagrams for clear and precise visualization of the measurement data. Finally, we show through case studies of two applications CalculiX and JuKKR that our workflow enables detailed performance analysis and is still easy to use.
Scientific presentation at the PDSW workshop
“User-Centric System Fault Identification Using IO500 Benchmark”
Monday, 15 November 20219am – 5:30pm CST
Radita Liem, Dmytro Povaliaiev, Jay Lofstead, Julian Kunkel, Christian Terboven
Predicting the performance of IO operations on current HPC systems where users competitively saturate the IO infrastructure is a major challenge. The first step towards this is to measure IO performance on HPC storage systems, which can be done using the IO500 benchmark.
This scientific talk presents a first step for a user-centric workflow that will be evaluated on the RWTH cluster CLAIX-2018. It is based on measurements of the IO500 benchmark and aims to optimize the IO performance. For this purpose, the best- and worst-case performance results for bandwidth and metadata rate are determined using the IO500 benchmark and presented as a bounding box. Users’ HPC applications are mapped within this box, illustrating the potential and direction of individual IO optimization.
Scientific talk at the Correctness Workshop
“Understanding the Performance of Dynamic Data Race Detection”
Friday, 19 November 202110:30am – 10:50am CST
Joachim Protze, Isabel Thärigen, Jonas Wahle
In this work, we apply performance analysis techniques to understand the cause of the drastic runtime overhead of data race detection. First, we propose a new problem class for SPEC OMP 2012. To analyze the runtime overhead, which can increase the execution time of programs by more than 80 times, we cannot start with a base runtime of one hour.We then use our newly proposed input dataset to study the significant runtime overhead of dynamic data race detection for specific applications. Using techniques from performance analysis, we can identify the root cause. Finally, we propose a modification to ThreadSanitizer that limits the runtime overhead for these applications to less than 40x.
JARA-CSD is Guest at the Booth of Jülich Supercomputing Centre (JSC)
As part of the “Jülich Aachen Research Alliance”, the HPC group is guest at the (virtual) booth of the Jülich Supercomputing Centre (JSC). To this end, the HPC group present their activities in the context of the JARA Center for Simulation and Data Science (JARA-CSD). Videos inform the attendees about current developments in MPI and OpenMP, as well as about tools for the correctness analysis of parallel programs and the most recent activities of the Standard Performance Evaluation Corporation (SPEC). Details on the release of the SPEC benchmarks can also be found in our Announcements section.
Furthermore, the booth provides interactive documents on topics such as NHR4CES, CLAIX, JARA-CSD and JARA SimLabs.
Visit us at the booth on the virtual exhibitor floor of Forschungszentrum Jülich.
You can find much more information and registration on the SC21 website.
We wish our HPC team good luck with their presentations, a lively exchange with the participants and a lot of new knowledge around HPC.
Responsible for the content of this article are Sandra Wienke and Janin Vreydal.
